1. Field of the Invention
The invention relates to digital processors, and more particularly, to digital processors for rapidly interpreting multiple virtual instruction sets.
2. Description of the Prior Art
Most electronic digital processors include a number of registers, an arithmetic logic unit, a number of counters, and a number of data paths or data buses which are interconnected to permit efficient execution of stored program instructions. However, the registers, data paths, arithmetic logic unit, and counters are ordinarily of a fixed width. That is, they are capable of storing, transferring, counting, or operating upon only operands which have a fixed number of bits. Operands which have a fixed number of bits are referred to as fixed length operands. Known microprogrammed processors, which have only fixed width data paths, registers, etc., present programming problems if data manipulations are required which involve operands having fewer bits or more bits than the number of bits readily accommodated by the fixed width registers, counters, data paths, etc., of the processor. Additional programming steps are required in order to perform shifting and/or masking of operands which have different lengths than the fixed length of the processor's data paths, registers, etc. Additional programming steps are often also required to perform iterative operations and to save carry bits. Such additional shifting, masking, carry save, and iterative operation necessitate additional firmware memory to store additional microinstructions. Further, additional machine cycles are required to execute the microinstruction subroutines necessary to perform the above shifting, masking, etc., operations. As will be shown hereinafter, the above constraints substantially increase the burden on the firmware programmer for processors which are microprogrammed to interpret multiple virtual instruction sets which have operands of different lengths than the fixed width data paths and fixed width registers of the processor.
Microprogrammed digital processors may be programmed to interpret multiple virtual instruction sets and to "emulate" one or more foreign computers, or target computers. In other words, such microprogrammed processors may be programmed to interpret and process user programs written for various other computers. Such programs may be written in different programming languages which have various formats in which the op codes, address fields, data fields, etc., have different lengths which are incompatible with the fixed widths of the registers, data paths, and execution units of the processor. Such processors are ordinarily microprogrammed machines which must be programmed at the firmware level to be able to efficiently execute the above programs written in the various user programming languages. In certain instances it may be highly desirable that programs initially written for one computer system do not have to be rewritten at substantial expense for another computer system. The user programs for such microprogrammed computers are written using high level languages such as Fortran, Cobol, etc. The computer's compiler then compiles a program of initial instructions. The virtual instructions, however, are not decoded by the computer hardware, but instead are interpreted by various firmware subroutines written from microinstructions. The microinstructions have op codes which are decoded to produce control signals which directly control the operation of the processor hardware. The term "firmware" refers to instructions or groups of instructions which are used to interpret the virtual instructions. Virtual instructions are instructions which are not directly executed by processor hardware. Instead, they are "interpreted" by firmware microinstructions.
A firmware program which is used to interpret a program written for a foreign machine is called an emulator. If the languages which the emulator program is designed to interpret are substantially different in format from the formats accommodated by the processor hardware, the emulator programs may be very lengthy and unwieldy. The cost of the firmware programming effort in such instances may be very high. The firmware programming effort for a microprogrammed processor capable of interpreting multiple virtual instruction sets is a substantial part of the total effort of developing such a processor. For example, for a machine which interprets five virtual instruction sets (such as virtual instruction sets generated Fortran, Cobol, etc., compilers), it is necessary to develop five different sets of interpretive firmware, one for interpreting each virtual instruction set. The necessity of utilizing additional microinstruction subroutines for each of the virtual instructions for each of the five virtual instruction sets at the firmware level to shift and/or mask or save carries of or perform iterative operations on every operand to make it compatible with the fixed width hardware greatly increases the burden on the firmware programmer. Thus, the programmer writing the emulator program has to be constantly concerned with the fixed width character of the processor hardware. He has to write additional firmware subroutines in order to manipulate each operand or field of a virtual instruction into a format such that it is of suitable width and is properly aligned to be compatible with the machine hardware. Further, the amount of high speed microinstruction storage memory required is substantially increased. The physical size of the firmware storage unit, which is ordinarily a relatively expensive, high speed random access memory, has necessarily been high for such processors. This is because increases in the physical size of a high speed memory inevitably increases the access time of the memory because of the concomitant increase in the duration of transmission line delays, which are in turn due to the increase in the lengths of the transmission lines necessitated by the increases in physical size. Further, the overall speed of execution of virtual instructions having formats incompatible with the processor hardware is decreased. This is because a relatively large number of processor machine cycles are required in order to shift and mask or save carriers, etc., of the various fields of the virtual instructions and data to convert them into formats which are compatible with the processor hardware. In short, the overall system cost in terms of great firmware programming development effort, the large amount of firmware storage, and the large number of required machine cycles to execute the above microinstruction subroutines has been substantial for systems capable of processing multiple virtual programs.
Although certain known microprogrammed processors have been designed having the capability of storing instructions with variable length operands in main memory, such processors have had fixed width internal data paths, registers, counters, arithmetic logic units, etc. For example, see the processor described in U.S. Pat. No. 3,739,352 entitled "Variable Word Width Processor Control" by R. E. Packard, issued June 12, 1973. Such processors have nevertheless required shifting, masking, carry save, and iterative operations performed by means of firmware subroutines in order to convert the format of such variable length operands fetched from main memory into formats compatible with the processor hardware. The main achievement of such machines has been to permit increased code compaction in main memory and auxiliary storage, thereby reducing the costs of such memory and auxiliary storage. However, such machines can only achieve such code compaction for instruction sets in which the instructions are bit-addressable at the main memory level.